Description: 1. ABOUT SYNTHESIS.- 1.1. Why VHDL?.- 1.2. VHDL for Which Purpose'?.- 1.3. Is VHDL a Good Language for Synthesise.- 1.4. A Book, an Outline.- 1.5. Synthesis Domain.- 1.6. Interests of Synthesis.- 1.7. Architectural Synthesis Versus Logic Synthesis.- 1.8. Consistency Between Simulation and Synthesis.- 2. VHDL CONCEPTS.- 2.1. Philosophy of the Language.- 2.2. Hardware Hierarchy.- 2.3. Software Hierarchy.- 2.4. Objects of the Language.- 2.5. Information Representation.- 2.6. Concurrency.- 2.7. Sequential Domain.- 2.8. Attached Characteristics.- 2.9. Predefined Environment.- 3. MAPPING VHDL TO HARDWARE.- 3.1. Synthesis Modeling Style.- 3.2. VHDL Types.- 3.3. VHDL Objects.- 3.4. Sequential Statements.- 3.5. Concurrent Statements.- 3.6. Using Generics.- 3.7. Conclusion.- 4. MAPPING HARDWARE TO VHDL.- 4.1. Combinational Circuits.- 4.2. Synchronous Circuits.- 5. DESIGN METHODOLOGY.- 5.1. Synthesis Design Cycle.- 5.2. Synthesis Process Control.- 6. SYNTHESIS STANDARD ENVIRONMENT.- 6.1. Principle.- 6.2. Package STD_LOGIC_1164.- 6.3. Synthesis Working Group Results.- 7. CASE STUDY.- 7.1. Traffic Light Controller: Once Again?.- 7.2. Specification of the Problem.- 7.3. Entity Declaration.- 7.4. Describing the Behavioral Architecture.- 7.5. Describing the Synthesizable Architecture.- 7.6. Designer's Concerns.- 8. APPENDIX.- 8.1. Grammar Summary.- 8.2. Memo.- 8.3 Index.

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