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Circuit Synthesis With Vhdl

by Jean-Michel Berge

Circuit Synthesis With Vhdl cover
  • ISBN: 9780792394297
  • ISBN10: 0792394291

Circuit Synthesis With Vhdl

by Jean-Michel Berge

  • List Price: $249.00
  • Binding: Hardcover
  • Publisher: Kluwer Academic Pub
  • Publish date: 01/01/1994
  • ISBN: 9780792394297
  • ISBN10: 0792394291
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Description: 1. ABOUT SYNTHESIS.- 1.1. Why VHDL'.- 1.2. VHDL for Which Purpose'''.- 1.3. Is VHDL a Good Language for Synthesise.- 1.4. A Book, an Outline.- 1.5. Synthesis Domain.- 1.6. Interests of Synthesis.- 1.7. Architectural Synthesis Versus Logic Synthesis.- 1.7.1. Technologies of Logic and Architectural Synthesis.- 1.7.2. Implications on Design Methodology.- 1.8. Consistency Between Simulation and Synthesis.- 2. VHDL CONCEPTS.- 2.1. Philosophy of the Language.- 2.1.1. Generality.- 2.1.2. Time.- 2.1.3. Modularity.- 2.1.4. Portability.- 2.2. Hardware Hierarchy.- 2.2.1. Entity/Architecture.- 2.2.2. Direct Instantiation of Entity.- 2.2.3. Notion of Component.- 2.2.4. Component Declaration.- 2.2.5. Component Instantiation.- 2.2.6. Component Configuration.- 2.2.7. Concurrent Procedure Call.- 2.3. Software Hierarchy.- 2.3.1. Writing Software.- 2.3.2. Packages.- 2.3.3. Subprograms.- 2.4. Objects of the Language.- 2.4.1. Constants.- 2.4.2. Variables.- 2.4.3. Signal.- 2.4.4. Files.- 2.5. Information Representation.- 2.5.1. Types of Objects.- 2.5.2. Scalar Types.- 2.5.3. Composite Types.- 2.5.4. Object Classes.- 2.6. Concurrency.- 2.6.1. Informal Definition.- 2.6.2. Signals and Ports.- 2.6.3. Resolution Function.- 2.6.4. Process.- 2.6.5. Other Concurrent Statements.- 2.6.6. Guarded Blocks.- 2.7. Sequential Domain.- 2.8. Attached Characteristics.- 2.9. Predefined Environment.- 2.9.1. Predefined Environment of the Language Itself.- 2.9.2. Standard Environment.- 2.9.3. "Proprietary" Environment.- 3. MAPPING VHDL TO HARDWARE.- 3.1. Synthesis Modeling Style.- 3.2. VHDL Types.- 3.2.1. Supported Type Declarations.- 3.2.2. Predefined Types.- 3 2 3 IEEE Strongly Recommended Types.- 3.2.4. Unsupported Types.- 3.2.5. Subtypes.- 3.3. VHDL Objects.- 3.3.1. Constants.- 3.3.2. Variables Versus Signals.- 3.3.3. Initial Values.- 3.3.4. Arithmetic Operators.- 3.4. Sequential Statements.- 3.4.1. Variable Assignment.- 3.4.2. Signal Assignment.- 3.4.3. Synchronization Statement.- 3.4.4. Conditional Statement.- 3.4.5. Iterative Statement.- 3.4.6. Subprogram Call.- 3.5. Concurrent Statements.- 3.5.1. Process and Synchronization Statement.- 3.5.2. Signal Assignment.- 3.5.3. Component Instantiation.- 3.5.4. Block Statement.- 3.5.5. Concurrent Procedure Call.- 3.5.6. Generate Statement.- 3.6. Using Generics.- 3.7. Conclusion.- 4. MAPPING HARDWARE TO VHDL.- 4.1. Combinational Circuits.- 4.1.1. Logic Gates.- 4.1.2. Comparators.- 4.1.3. Arithmetic Operations.- 4.1.4. Shift and Rotate Operations.- 4.1.5. Multiplexers.- 4.1.6. ALU.- 4.1.7. Three-State Logic.- 4.1.8. ROM.- 4.1.9. PLA.- 4.2. Synchronous Circuits.- 4.2.1. Latches.- 4.2.2. Registers.- 4.2.3. Synchronous Counters.- 4.2.4. Memories.- 4.2.5. Finite State Machines.- 5. DESIGN METHODOLOGY.- 5.1. Synthesis Design Cycle.- 5.1.1. Design Cycle Steps.- 5.1.2. Modeling for Synthesis.- 5.1.3. Synthesis Process.- 5.1.4. Final Validation.- 5.2. Synthesis Process Control.- 5.2.1. What Is Synthesis Process Control'.- 5.2.2. Design Constraints.- 5.2.3. Interface Formats.- 6. SYNTHESIS STANDARD ENVIRONMENT.- 6.1. Principle.- 6.2. Package STD_LOGIC_1164.- 6.2.1. Logic Type Interpretation: Simulation Semantics.- 6.2.2. Description of Package STD_LOGIC_1164.- 6.3. Synthesis Working Group Results.- 6.3.1. Logic Type Interpretation: Synthesis Semantics.- 6.3.2. Arithmetic Packages.- 6.3.3. Special Identifications.- 7. CASE STUDY.- 7.1. Traffic Light Controller: Once Again'.- 7.2. Specification of the Problem.- 7.3. Entity Declaration.- 7.4. Describing the Behavioral Architecture.- 7.5. Describing the Synthesizable Architecture.- 7.5.1. From Behavioral To Synthesizable Description.- 7.5.2. First Proposition of Synthesizable Architecture.- 7.5.3 Second Proposition of Synthetizable Architecture.- 7.6. Designer''s Concerns.- 7.6.1. Tool Dependency.- 7.6.2. Constraint Checking.- 8. APPENDIX.- 8.1. Grammar Summary.- 8.2. Memo.- 8.2.1. Process: Is Inferred Hardware Combinational or Sequential'.- 8.2.2. Combinational Circuits: Logic Gates.- 8.2.3. Combinational Circuits: Multiplexers.- 8.2.4. Combinational Circuits: Three-State Operators.- 8.2.5. Sequential Circuits: Latch and Register.- 8.2.6. Sequential Circuits: Counter with Reset.- 8.2.7. Sequential Circuits: Finite State Machine.- 8.3 Index.
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