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Digital Timing Macromodeling for Vlsi Design Verification

by Jeong-Taek Kong

Digital Timing Macromodeling for Vlsi Design Verification cover
  • ISBN: 9780792395805
  • ISBN10: 0792395808

Digital Timing Macromodeling for Vlsi Design Verification

by Jeong-Taek Kong

  • List Price: $259.00
  • Binding: Hardcover
  • Publisher: Kluwer Academic Pub
  • Publish date: 05/01/1995
  • ISBN: 9780792395805
  • ISBN10: 0792395808
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Description: List of Figures. List of Tables. Preface. 1. Introduction. 2. Survey of Simulation and Macromodeling Techniques. 3. A Nonlinear Macromodel. 4. Reduction Techniques for Complex Gates. 5. Accounting for RC- Interconnects. 6. Transmission Gate Modeling. 7. Conclusions. A. The SPICE Level 2 Model. B. Nonlinear Macromodel Output Response Derivations. C. The Derivation of M = 0.5 Heuristic in Reduction Techniques. D. Delay Errors for Various AOI Gates. References. Index.
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