Hierarchical Modeling for Vlsi Circuit Testing
- List Price: $179.00
- Binding: Hardcover
- Publisher: Kluwer Academic Pub
- Publish date: 02/01/1990
Description:
1 Introduction.- 1.1 Background.- 1.2 Prior Work.- 1.3 Outline.- 2 Circuit and Fault Modeling.- 2.1 Vector Sequence Notation.- 2.2 Circuit and Fault Models.- 2.3 Case Study: k-Regular Circuits.- 3 Hierarchical Test Generation.- 3.1 Vector Cubes.- 3.2 Test Generation.- 3.3 Implementation and Experimental Results.- 4 Design for Testability.- 4.1 Ad Hoc Techniques.- 4.2 Level Separation (LS) Method.- 4.3 Case Study: ALU.- 5 Concluding Remarks.- 5.1 Summary.- 5.2 Future Directions.- Appendix A: Proofs of Theorems.- A.1 Proof of Theorem 3.2.- A.2 Proof of Theorem 3.3.- A.3 Proof of Theorem 4.1.
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