Description: 1 Introduction.- 1.1 Approaches to Yield Modeling.- 2 Defect Semantics and Yield Modeling.- 2.1 Microelectronics Technology.- 2.2 Modeling of Process Induced Defects and Faults.- 2.3 Statistical Characterization of Spot Defects.- 2.4 Brief Overview of Historical Yield Models.- 3 Computational Models for Defect-Sensitivity.- 3.1 Taxonomy of Defect--Sensitivity Models.- 3.2 Theoretical Foundation of Critical Areas.- 3.3 Susceptible Sites.- 3.4 Critical Regions and Critical Areas.- 3.5 Geometrical Proof of the Construction of Critical Regions..- 4 Single Defect Multiple Layer (SDML) Model.- 4.1 Critical Regions for Protrusion Defects.- 4.2 Critical Regions for Isolated Spot Defects.- 4.3 Critical Regions for Intrusion Defects.- 4.4 A CAD System for SDML Critical Areas.- 4.5 A "Spot-Defect" Language.- 4.6 Layout Partitioning.- 4.7 Extraction of Multi--Layer Susceptible Sites.- 4.8 Defect Mechanisms.- 4.9 Intrusion Defects.- 4.10 Isolated--Spot Defects.- 4.11 Protrusion Defects.- 4.12 Construction of Multi--Layer Critical Regions.- 4.13 Computation of Multi--Layer Critical Areas.- 4.14 Notes on Implementation.- 4.15 Examples.- 5 Fault Analysis and Multiple Layer Critical Areas.- 5.1 Failure Analysis and Yield Projection of 6T--RAM Cells.- 5.2 Fault Weighting.- 5.3 Analysis and Weighting of Defect Induced Faults.- 6 Single Defect Single Layer (SDSL) Model.- 6.1 Theory of Critical Regions for SDSL Models.- 6.2 Single--Layer Susceptible Sites.- 6.3 Critical Regions for Bridges.- 6.4 Critical Regions for Cuts.- 6.5 Computation of Critical Areas for SDSL Models.- 6.6 Extraction of SDSL Susceptible Sites.- 6.7 Computation of SDS Critical Areas.- 6.8 Complexity Analysis.- 6.9 Examples.- 7 IC Yield Prediction and Single Layer Critical Areas.- 7.1 Sensitivity Analysis.-7.9 Yield Analysis.- 8 Single vs. Multiple Layer Critical Areas.- 8.1 Uncovered Situations of the SDSL Model.- 8.2 Case Study.- 8.2.1 Comparative Results.- 8.3 Summary and Discussion.- References.- Appendix 1 Sources of Defect Mechanism.- Appendix 2 End Effects of Critical Regions.- Appendix 3 NMOS Technology File.

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