Description: 1 Introduction.- 1.1 Introduction to the VHDL Language.- 1.2 Multi-Level Design.- 1.3 The Model Accuracy Continuum.- 2 Anatomy of a VHDL Model.- 2.1 Describing Electronic Hardware in VHDL.- 2.2 A VHDL File.- 2.3 The Standard Logic Package.- 2.4 User Defined Packages.- 2.5 VHDL Models and the Accuracy Continuum.- 2.6 Handling Timing Using Configurations.- 2.7 Using VHDL as a Stimulus Language.- 2.8 Standardized VHDL Modelling Conventions.- 3 Combinational Devices.- 3.1 Simple Gates.- 3.2 Selectors/Multiplexers.- 3.3 Switch Level Devices.- 3.4 Simple ALU's.- 3.5 One Shots.- 3.6 Comparators.- 3.7 Parity Generators/Checkers.- 4 Sequential Devices.- 4.1 Flip-Flops.- 4.2 Registers.- 4.3 Counters.- 5 Memory Devices.- 5.1 Memory Initialization.- 5.2 Read Only Memories.- 5.3 Random Access Memories.- 5.4 PALs, PLDs.- 6 Complex Devices.- 6.1 Getting Started.- 6.2 The Timing Model.- 6.3 Error Handling.- 6.4 Techniques for Modeling.- 6.5 Quality Assurance.- 7 The Standard Logic Package.- 7.1 Using the Standard Logic Package.- 7.2 The Logic Value System.- 7.3 Technology Rules.- 7.4 Bus Resolution.- 7.5 Logic Manipulation.- 7.6 Timing Utilities.- 7.7 Integer Data Utilities.

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