Description: 1 Introduction and Motivation.- 1.1 Wave Pipelining.- 1.2 History.- 1.3 Designing Wave Pipelined Circuits.- 1.4 Organization.- 2 Clock Period Constraints: Single Stage Systems.- 2.1 Introduction.- 2.2 System Model.- 2.3 Constraints for Correct Clocking.- 2.4 Minimizing the Clock Period.- 2.5 The Parameter k.- 2.6 Special Cases.- 2.7 Conclusions.- 3 Clock Period Constraints: Multiple Stage Systems.- 3.1 Introduction.- 3.2 System Model.- 3.3 Constraints for Correct Clocking.- 3.4 Example.- 3.5 Conclusions.- 4 Exact Timing Analysis.- 4.1 Introduction.- 4.2 Motivation and Justification.- 4.3 Complexity of Problem.- 4.4 Notation and Model.- 4.5 Basic Algorithm Development.- 4.6 Conclusion.- 5 Exact Timing Analysis: Algorithm.- 5.1 Introduction.- 5.2 Algorithm Strategy.- 5.3 Calculation of Output Responses.- 5.4 Verification of Output Responses.- 5.5 Detection of Components.- 5.6 Vector Reporting.- 5.7 Implementation.- 5.8 Limitations and Extensions.- 5.9 Conclusion.- 6 Practical Considerations in Wave Pipelining.- 6.1 Architecture Choice.- 6.2 Path Delay Variation.- 6.3 Circuit Choice.- 6.4 Parametric Variations due to Manufacturing and Environmen-tal Factors.- 6.5 Clock Distribution and Physical Layout.- 6.6 Technology Scaling.- 6.7 Conclusion.- 7 Design Examples.- 7.1 Introduction.- 7.2 Parallel-Carry Adder.- 7.3 Sampler.- 7.4 Conclusion.- 8 Conclusions.- A Example Model File.- B Calculation of Tolerance of Parametric Variations.- References.

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